VMX Capabilities
An enumeration that represents the available VMX capabilities.
Overview
The capabilites available to the hypervisor can vary depending on the specific hardware platform or OS release. Use the hv_vmx_read_capability(_:_:) API at run time to determine the capabilities that can you can select.
The example below demonstrates the process for checking for the availability a specific capability, here checking for the avaiability of timestamp-counter scaling (TSC scaling):
static uint64_t canonicalize(uint64_t ctrl, uint64_t mask) {
return (ctrl | (mask & 0xffffffff)) & (mask >> 32);
}
main() {
// Fetch the supported capabilities for the PROCBASED2 field
if (hv_vmx_read_capability(HV_VMX_CAP_PROCBASED2, &proc2_cap) != 0)
errx(1, "vcpu_read_capability(%u, CAP_VMX_PROCBASED2) failed", vcpu);
// Apply the constraints to our request to use TSC scaling
const uint64_t newcap = canonicalize(CPU_BASED2_TSC_SCALING, proc2_cap);
// Test to see if that bit is supported on this platform
if ((newcap & CPU_BASED2_TSC_SCALING) == 0) {
warnx(“TSC scaling not supported on this platform”);
}
// Continue, but without TSC scaling ...
write_vmcs(vcpu, VMCS_CTRL_CPU_BASED2, newcap);
// ...
}
Topics
Capabilities
PIN_BASED_INTRPIN_BASED_NMIPIN_BASED_VIRTUAL_NMIPIN_BASED_PREEMPTION_TIMERPIN_BASED_POSTED_INTRCPU_BASED_IRQ_WNDCPU_BASED_TSC_OFFSETCPU_BASED_HLTCPU_BASED_INVLPGCPU_BASED_MWAITCPU_BASED_RDPMCCPU_BASED_RDTSCCPU_BASED_CR3_LOADCPU_BASED_CR3_STORECPU_BASED_CR8_LOADCPU_BASED_CR8_STORECPU_BASED_TPR_SHADOWCPU_BASED_VIRTUAL_NMI_WNDCPU_BASED_MOV_DRCPU_BASED_UNCOND_IOCPU_BASED_IO_BITMAPSCPU_BASED_MTFCPU_BASED_MSR_BITMAPSCPU_BASED_MONITORCPU_BASED_PAUSECPU_BASED_SECONDARY_CTLSCPU_BASED2_VIRTUAL_APICCPU_BASED2_EPTCPU_BASED2_DESC_TABLECPU_BASED2_RDTSCPCPU_BASED2_X2APICCPU_BASED2_VPIDCPU_BASED2_WBINVDCPU_BASED2_UNRESTRICTEDCPU_BASED2_APIC_REG_VIRTCPU_BASED2_VIRT_INTR_DELIVERYCPU_BASED2_PAUSE_LOOPCPU_BASED2_RDRANDCPU_BASED2_INVPCIDCPU_BASED2_VMFUNCCPU_BASED2_VMCS_SHADOWCPU_BASED2_ENCLS_EXIT_MAPCPU_BASED2_RDSEEDCPU_BASED2_PMLCPU_BASED2_EPT_VECPU_BASED2_PT_CONCEAL_VMXCPU_BASED2_XSAVES_XRSTORSCPU_BASED2_EPT_MODE_BASED_EXECCPU_BASED2_EPT_SUBPAGE_WRITECPU_BASED2_PT_GUEST_PHYSICALCPU_BASED2_TSC_SCALINGCPU_BASED2_USER_WAIT_PAUSECPU_BASED2_ENCLV_EXIT_MAPVMX_EPT_VPID_SUPPORT_ADVMX_EPT_VPID_SUPPORT_EXONLYVMEXIT_SAVE_DBG_CONTROLSVMEXIT_HOST_IA32EVMEXIT_LOAD_IA32_PERF_GLOBAL_CTRLVMEXIT_ACK_INTRVMEXIT_SAVE_IA32_PATVMEXIT_LOAD_IA32_PATVMEXIT_SAVE_EFERVMEXIT_LOAD_EFERVMEXIT_SAVE_VMX_TIMERVMEXIT_CLEAR_IA32_BNDCFGSVMEXIT_PT_CONCEAL_VMXVMEXIT_CLEAR_IA32_RTIT_CTLVMEXIT_LOAD_CET_STATEVMENTRY_LOAD_DBG_CONTROLSVMENTRY_GUEST_IA32EVMENTRY_SMMVMENTRY_DEACTIVATE_DUAL_MONITORVMENTRY_LOAD_IA32_PERF_GLOBAL_CTRLVMENTRY_LOAD_IA32_PATVMENTRY_LOAD_EFERVMENTRY_LOAD_IA32_BNDCFGSVMENTRY_PT_CONCEAL_VMXVMENTRY_LOAD_IA32_RTIT_CTLVMENTRY_LOAD_CET_STATE