Contents

GIC registers

These registers support the operation of a generic interrupt controller and its interface with the Hypervisor and virtual CPUs.

Discussion

For more information on the purpose of specific register sets and their operation in GICs, see the ARM Generic Interrupt Controller (GIC) v3 architecture specification.

Topics

Distributor registers

Redistributor registers

Message signaled interrupt (MSI) registers

GIC CPU interface (ICC) registers

GIC virtual CPU interface (ICV) registers

GIC hypervisor virtual interface control (ICH) registers

Reserved interrupt identifiers

See Also

Generic interrupt controllers (GICs)